1. Field of the Invention
The present invention relates to a semiconductor device including a connection structure having two conductive patterns connected to each other through an insulative layer, a method for producing the same, and a display device including such a connection structure.
2. Description of the Related Art
As is well-known, there are various types of semiconductor devices. One type of semiconductor device is an active matrix liquid crystal display device. FIG. 13 is a block diagram illustrating an exemplary structure of a conventional active matrix liquid crystal display device.
The active matrix liquid crystal display device shown in FIG. 13 includes two substrates located opposed to each other and a liquid crystal layer interposed therebetween (not shown). One of the substrates (represented by chain line 110) includes a plurality of scanning lines 101 and a plurality of signal lines 102 which are arranged perpendicular to each other. A pixel electrode 103 is provided at each of intersections of the scanning lines 101 and the signal lines 102. Although not shown, the other substrate includes a counter electrode facing the pixel electrodes 103. The pixel electrodes 103 arranged along each scanning line 101 are commonly connected to the scanning line 101 via corresponding switching elements, and the pixel electrodes 103 arranged along each signal line 102 are commonly connected to the signal line 102 via corresponding switching elements.
The liquid crystal display device shown in FIG. 13 further includes a scanning line driving circuit 104, a control circuit 105, a voltage generation circuit 106, and a signal line driving circuit 107.
In one horizontal scanning period, the scanning line driving circuit 104 selects one of the scanning lines 101 in response to signals from the control circuit 105. Then, the scanning line driving circuit 104 applies one of voltages VGH and VGL from the voltage generation circuit 106 to the selected scanning line 101, and applies the other voltage VGH or VGL to the other scanning lines 101 which are not selected. In response to signals from the control circuit 105, the signal line driving circuit 107 applies the voltage VSL or VSH from the voltage generation circuit 106 to each of the signal lines 102. The voltage generation circuit 106 applies a common voltage COM to the counter electrode (not shown). In the next scanning period,. the scanning driving circuit 104 selects another one of the scanning lines 101. In this manner, the scanning lines 101 are sequentially selected and then the rest of the operation described above is performed.
Thus, the pixel electrodes 103 connected to each scanning line 101 are driven in each horizontal scanning period, and display corresponding to such pixel electrodes 103 is performed. In one frame, display corresponding to one image plane is performed.
In such an active matrix liquid crystal display device, the substrates are formed of quartz or glass. A switching element (not shown; e.g., thin film transistor) is provided in correspondence with each pixel electrode 103 for turning ON and OFF the pixel electrode 103. Recently, the scanning line driving circuit 104 and the signal line driving circuit 107 are integrated on the substrate in order to reduce the cost and the size of the liquid crystal display device.
A liquid crystal display device having the driving circuits integrated on the substrate is disclosed in, for example, SID ""96 DIGEST, pp. 17-20. In the liquid crystal display device disclosed in the abovementioned publication, lines which include areas to be gate electrodes of the thin film transistors are anodized. Thus, generation of hillocks and the like is prevented even when the gate electrodes are formed of aluminum-type metal materials having a relatively low resistance; and the offset length of the thin film transistors is controlled at a satisfactorily high precision. Accordingly, the operation of the thin film transistors is stabilized.
In response to a demand for a highly integrated structure, some active matrix liquid crystal display devices adopt a connection structure, in which a plurality of conductive layers are laminated with insulative layers interposed therebetween and the conductive layers are connected to one another through an opening (contact hole) in each of the insulative layers.
FIG. 14A is a plan view of a conventional connection structure included in a semiconductor device, and FIG. 14B is a cross-sectional view of the connection structure taken along line C-Cxe2x80x2 in FIG. 14A. The connection structure shown in FIGS. 14A and 14B includes a first conductive layer 111, an interlayer insulative layer 112 and a second conductive layer 113 which are sequentially laminated. The second conductive layer 113 is connected to the first conductive layer 111 through an opening 112a formed in the interlayer insulative layer 112. The opening 112a has a smaller planar size than that of each of the first and second conductive layers 111 and 113, and the opening 112a is substantially completely covered by the second conductive layer 113.
As shown in FIG. 14A, the conventional connection structure has a connection section 114 in which the first conductive layer 111 and the second conductive layer 113 are connected to each other. The connection section 114 is set to have a larger planar size than that of the opening 112a in consideration of the precision with which the first and second conductive layers 111 and 113 can be positioned with respect to the opening 112a and also in consideration of the displacement of the layers 111, 112 and 113 caused during etching, which is performed for patterning the layers 111, 112 and 113.
According to the design rule adopted in a usual semiconductor fabrication process, where the alignment margin or design margin is xcex, the minimum width of the pattern of a conductive layer is 2xcex and the distance between two adjacent patterns of the conductive layer is 2xcex. In the case of the display device shown in FIGS. 14A and 14B, the minimum value for width W1 of a pattern of the second conductive layer 113 (hereinafter, referred to the xe2x80x9csecond conductive layer pattern 113xe2x80x9d for simplicity) is 2xcex, and alignment margin M1 required. for each of two ends of the second conductive layer pattern 113 in the width direction is xcex. The connection section 114 needs to be extended in the width direction beyond edges 113a and 113b of the second conductive layer pattern 113 so as to accommodate the two alignment margins (2xcex). The distance between two adjacent second conductive layer patterns 113 (only one is shown in FIGS. 14A and 14B) in the width direction is 2xcex. As a result, a width of 8xcex is required to provide one second conductive layer pattern 113. In the case where a plurality of second conductive layer patterns 113 are arranged as shown in FIG. 15, the pitch of the second conductive layer patterns 113 is at least 5xcex (sum of the width 2xcex of each second conductive layer pattern 113, the alignment margin xcex and the distance 2xcex between one connection section 114 and an adjacent second conductive layer pattern 113).
In the case where the driving circuits are integrated on one substrate as described above, output stages of a driving circuit are provided in correspondence with the scanning lines and/or the signal lines. The output stages need to be arranged at the same pitch as that of the pixel electrodes, which requires an increased density of lines and other elements. Especially in the fields of high precision liquid crystal panels and liquid crystal panels to be used in conjunction with projectors, the pitch of the pixel electrodes is sometimes as small as 30 xcexcm or less. Accordingly, the connection section 114 is demanded to have a minimum possible width.
In order to anodize the gate electrodes of the thin film transistors as described above, a DC voltage needs to be applied between the gate electrodes and the anodizing solution (a solution of tartaric acid or oxalic acid), in which the gate electrodes are immersed. In order to apply the DC voltage, the gate electrodes need to be commonly connected to an application terminal of the DC voltage and then separated from one another after the anodization.
A conventional method for producing a connection structure including anodization of gate electrodes will be described with reference to FIGS. 16A, 16B, 17A, 17B, 18A, 18B, 19, 20A and 20B.
A first conductive layer is patterned by a first patterning step as shown in FIG. 16A (plan view) and FIG. 16B (cross-sectional view), thereby forming a line pattern 123 including areas 121 and 122 to be gate electrodes. (The areas 121 and 122 to be gate electrodes will be referred to xe2x80x9cthe gate electrodes 121 and 122xe2x80x9d for simplicity.) The gate electrodes 121 and 122 are anodized by applying a DC voltage between the gate electrodes 121 and 122 and an anodizing solution in which the gate electrodes 121 and 122 are immersed in the state where the gate electrodes 121 and 122 as included in the line pattern 123 are commonly connected to an application terminal of the DC voltage.
Next, as shown in FIG. 17A (plan view) and FIG. 17B (cross-sectional view), intermediate areas between the gate electrodes 121 and 122 are removed by a second patterning step, thereby electrically separating the gate electrodes 121 and 122 from each other.
Then, as shown in FIG. 18A (plan view) and FIG. 18B (cross-sectional view), an interlayer insulative layer 124 is formed so as to cover the gate electrodes 121 and 122, and openings 124a are formed in the interlayer insulative layer 124.
As shown in FIG. 19, a second conductive layer 125 is formed so as to cover the interlayer insulative layer 124 and the gate electrodes 121 and 122, and is patterned as shown in FIG. 20A (plan view) and FIG. 20B (cross-sectional view).
According to this method, the gate electrodes 121 and 122 are anodized and then patterned, which requires two-stage patterning. Therefore, photolithography and etching need to be performed one extra time compared to the method for producing a thin film transistor without anodization. The extra step of photolithography and etching increases the production cost and reduces the production yield. Under these circumstances, a method for producing a thin film transistor including the step of anodizing gate electrodes without requiring such an extra step has been demanded.
According to one aspect of the invention, a semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The second conductive layer is connected to the first conductive layer through the opening. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.
In one embodiment of the invention, a connection section in which an area of the first conductive layer and an area of the second conductive layer which are connected to each other ha s a smaller planar size than a planar size of the opening.
In one embodiment of the invention, the second conductive layer covers at least a part of a periphery of the opening.
In one embodiment of the invention, the first conductive layer and the second conductive layer are formed of a metal material
In one embodiment of the invention, the first conductive layer has an anodized layer on at least a part of a side surface thereof.
According to another aspect of the invention, a method for producing a semiconductor device includes the steps of forming a first conductive layer; forming an interlayer insulative layer on the first conductive layer and forming an opening in the interlayer insulative layer; forming a second conductive layer on the first conductive layer so as to cover the interlayer insulative layer; and patterning the second conductive layer. The step of patterning the second conductive layer also patterns an area of the first conductive layer located in the opening.
In one embodiment of the invention, the step of patterning the second conductive layer patterns the second conductive layer so as to partially cover the opening.
In one embodiment of the invention, the step of patterning the second conductive layer electrically divides the first conductive layer into at least two at the opening.
In one embodiment of the invention, the step of forming the first conductive layer includes the steps of patterning the first conductive layer and anodizing the first conductive layer, and the step of patterning the second conductive layer also patterns the first conductive layer having an anodized layer on a surface thereof.
In one embodiment of the invention, the step of patterning the second conductive layer is performed by dry etching.
According to still another aspect of the invention, a display device has a connection structure. The connection structure includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The second conductive layer is connected to the first conductive layer through the opening. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.
In one embodiment of the invention, a display device includes a first substrate including a plurality of scanning lines, a plurality of signal lines, a plurality of pixel electrodes respectively provided at intersections of the scanning lines and the signal lines, and a plurality of switching elements respectively for connecting the pixel electrodes to the scanning lines and the signal lines; a second substrate including a counter electrode; a liquid crystal layer interposed between the first substrate and the second substrate; and a driving circuit for supplying a voltage to the plurality of pixel electrodes and the counter electrode to drive the liquid crystal layer. The plurality of scanning lines are formed of the first conductive layer and have an anodized layer on-at least a part of a side surface thereof.
In one embodiment of the invention, the driving circuit is provided on the first substrate and includes the connection structure.
Thus, the invention described herein makes possible the advantages of (1) providing a semiconductor device including a connection structure having a connection section which has a reduced planar size, a method for producing the same, and a display device including such a connection structure; and (2) a semiconductor device which includes a connection structure and is produced by a simplified method even when one of two conductive layers is anodized, and such a simplified method.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.